1. Field of the Invention
The present invention relates to a delay control circuit capable of adjusting the delay time of a signal, and more particularly, to a delay control circuit capable of controlling the rising edge delay time and the falling edge delay time of a signal, respectively.
2. Description of the Related Art
In coordination with a high speed digital transfer interface for delivering data, usually, a timing of a sampling control signal is demanded, by which the receiving terminal performs sampling operations. The timing is in charge of coordinating the delivering data at a transmission terminal and the sampling data at a receiving terminal and works based on a predetermined rule (for example, triggered by the rising edge of the sampling control signal or triggered by the falling edge of the sampling control signal), so as to ensure the maximum setup capacity and keep a proper time margin.
In practice, the sampling control signal adjusts slightly the delay time at the transmission terminal or the receiving terminal to maintain a proper time margin. In the prior art, the delay of a sampling control signal is usually performed by a programmable delay cell or a delay lock loop. However, regardless of a programmable delay cell or using a delay lock loop, both the rising edge and falling edge of the sampling control signal have the same delay time. In other words, the rising edge delay time would be equal to the falling edge delay time after performing a delay time adjustment on the sampling control signal.
The above-mentioned adjustment scheme is appropriate to such a system where a single edge (rising edge or falling edge) is used. However, in a high speed system, for example the system adopting the Ultra DMA (DMA standing for direct memory access) transfer mode in its ATA (AT attachment standard) interface or the DDR SDRAM system, both the rising edge or falling edge of a sampling control signal are used for triggering in transferring data. Therefore, a conventional delay circuit is not competent for delaying a sampling control signal where the time margins both of the rising edge and the falling edge must be taken into account.
FIG. 1 is a schematic drawing of a conventional delay control circuit. The delay control circuit 200 herein includes delay units 212 and 214, an AND gate 222, an OR gate 224 and a selector 230. Wherein the delay units 212 and 214 form a delay unit 210, and the AND gate 222 and the OR gate 224 form a signal regulation unit 220. An input signal INT is delayed by the delay unit 212 with the delay time of (DA+DB) to generate a delayed input signal DS1 and is delayed by the delay unit 214 for the delay time of DB to generate a delayed input signal DS2. Both the delayed input signal DS1 and the delayed input signal DS2 are processed by the AND gate 222 to output a rising edge delay signal DRS that delays the rising edge of the input signal INT for the delay time of (DA+DB) and falling edge of the input signal INT for the delay time of DB, while processed by the OR gate 224 to output a falling edge delay signal DFS that delays the rising edge of the input signal INT with the delay time of DB and falling edge of the input signal INT with the delay time of (DA+DB). Then, the selector 230 decides whether the output signal is the rising edge delay signal DRS or the falling edge delay signal DFS according to a control signal CS.
FIG. 2A is the excerpted drawing of a delay control circuit according to the U.S. Pat. No. 6,424,197. The delay control circuit 100 herein includes a delay unit 110 and a signal regulation unit 120. The delay unit 110 outputs delayed input signals DS1 and DS2 to the signal regulation unit 120 according to control signals dr[2:0] and df[2:0]. After the logic operations, the signal regulation unit 120 generates an output signal OUT by delaying the rising edge of the input signal INT with delay time of DR and falling edge of the input signal with delay time of DF. Wherein, if the output of a comparison circuit 122 is a low logic level (DF>DR), the output signal OUT is the result of an ‘OR’ logic operation on the delayed input signals DS1 and DS2; if the output of a comparison circuit 122 is a high logic level (DR>DF), the output signal OUT is the result of an ‘AND’ logic operation on the delayed input signals DS1 and DS2.
FIG. 2B is the excerpted diagram of a delay unit according to the U.S. Pat. No. 6,424,197. As shown by FIG. 2B, a plurality of buffers are in series connection to delay the input signal INT, wherein each buffer adds a different delay time to the input signal INT which comes in the buffer and then is output. After that, the multiplexers in FIG. 2C output the required delayed input signals DS1 and DS2 according to the control signals dr[2:0] and df[2:0]. The signal regulation unit 120 in FIG. 2C generates the output signal OUT according to the delayed input signals DS1 and DS2, wherein an ‘AND’ logic operation or an ‘OR’ logic operation on the delayed input signals DS1 and DS2 results in the output signal OUT.
In a practical application in anyone of the above-described delay control circuits of FIGS. 2A, 2B and 2C, if the delay time difference between DR and DF are larger than input signal pulse width, an error of the output signal OUT could occur. As shown in FIG. 2D, wherein W represents the pulse width of the input signal INT, DR and DF respectively represent the delay time of the rising edge and the falling edge of the input signal INT, the expected output signal from the signal regulation unit 120 should be illustrated by OUT1. However, due to the delayed input signals DS1 and DS2 outputted from the delay unit 110 having an excessive delay time difference there-between, the real output signal OUT2 of the signal regulation unit 120 has an error as shown by FIG. 2D, rather than the expected OUT1.
In particular, the delay unit 210 or 110 in FIGS. 1 and 2A is formed usually by a plurality of delayers in series connection to each other, and each of the delayers gives out an inconsistent delay time relying on the individual process condition. Such an uncertainty more likely causes an error of the output signal for slightly adjusting a high speed signal. Hence, if the delay time given by a conventional circuit is controlled more efficiently, a more stable output of a delay control circuit is expected, which would certainly benefit the delay control of high frequency signals.